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preliminary cy14b104k/cy14b104m 4 mbit (512k x 8/256k x 16) nvsram with real-time-clock cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-07103 rev. *i revised june 20, 2008 features 15 ns, 20 ns, 25 ns, and 45 ns access times internally organized as 512k x 8 (cy14b104k) or 256k x 16 (cy14b104m) hands off automatic store on power down with only a small capacitor store to quantumtrap ? nonvolatile elements is initiated by software, device pin, or autostore ? on power down recall to sram initiated by software or power up high reliability infinite read, write, and recall cycles 200,000 store cycles to quantumtrap 20 year data retention single 3v +20%, ?10% operation data integrity of cypress nvsram combined with full featured real-time-clock watchdog timer clock alarm with programmable interrupts capacitor or battery backup for rtc commercial and industrial temperatures 44/54-pin tsop ii package pb-free and rohs compliance functional description the cypress cy14b104k/cy14b104m combines a 4-mbit nonvolatile static ram with a full featured real-time-clock in a monolithic integrated circ uit. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolatile memory. the sram is read and written an infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. the real-time-clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. the alarm function is programmable for one time alarms or periodic seconds, minutes, hours, or days. there is also a programmable watchdog timer for process control. we oe ce v cc v ss v cap hsb cy14b104k v rtccap v rtcbat int x 1 x 2 bhe ble logic block diagram a 0 - a 18 address dq0 - dq7 cy14b104m [1] [1] note 1. address a 0 - a 18 and dq0 - dq7 for x8 configuration, address a 0 - a 17 and data dq0 - dq15 for x16 configuration. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 2 of 29 pinouts figure 1. pin diagram - 44/54 tsop ii pin definitions pin name io type description a 0 ? a 18 input address inputs used to select one of the 524, 288 bytes of the nvsram for x8 configuration . a 0 ? a 17 address inputs used to select one of the 262,144 bytes of the nvsram for x16 configuration . dq0 ? dq7 input/output bidirectional data io lines for x8 configuration . used as input or output lines depending on operation. dq0 ? dq15 bidirectional data io lines for x16 configuration . used as input or output lines depending on operation. nc no connect no connects. this pin is not connected to the die. we input write enable input, active low. when selected low, data on the io pins is written to the address location latched by the falling edge of ce . ce input chip enable input, active low. when low, selects the chip. when high, deselects the chip. oe input output enable, active low. the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the io pins to tri-state. bhe input byte high enable, active low . controls dq15 - dq8. ble input byte low enable, active low . controls dq7 - dq0. x 1 output crystal connection . drives crystal on start up. x 2 input crystal connection. for 32.768 khz crystal. v rtccap power supply capacitor supplied backup rtc supply voltage . left unconnected if v rtcbat is used. v rtcbat power supply battery supplied backup rtc supply voltage . left unconnected if v rtccap is used. nc a 8 x2 x1 v ss dq6 dq5 dq4 v cc a 13 dq3 a 12 dq2 dq1 dq0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 a 17 a 18 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) a 10 v rtcbat we dq7 hsb int v ss v cc v cap v rtccap (x8) a 17 dq7 dq6 dq5 dq4 v cc dq3 dq2 dq1 dq0 nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cap we a 8 a 10 a 11 a 12 a 13 a 14 a 15 a 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 54 - tsop ii top view (not to scale) oe ce v cc int v ss nc a 9 nc nc 54 53 52 51 49 50 hsb bhe ble dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 (x16) v rtccap v rtcbat x2 x1 [2] [2] [3] [3] notes 2. address expansion for 8 mbit. nc pin not connected to die. 3. address expansion for 16 mbit. nc pin not connected to die. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 3 of 29 device operation the cy14b104k/cy14b104m nvsram is made up of two functional components paired in the same physical cell. these are a sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferr ed to the nonvolatile cell (the store operation), or from the nonvolatile cell to the sram (the recall operation). using this unique architecture, all cells are stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the cy14b104k/cy14b104m supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 200k store operations. sram read the cy14b104k/cy14b104m pe rforms a read cycle whenever ce and oe are low, and we and hsb are high. the address specified on pins a 0-18 or a 0-17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle #1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle #2). the data output repeatedly responds to address changes within the t aa access time without the need for transi- tions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycle. the data on the common io pins io 0-7 are written into the memory if it is valid t sd before the end of a we controlled write or before the end of an ce controlled write. it is recommended that oe be kept high during the entire write cycle to avoid data bus contention on common io lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b104k/cy14b104m stores data to the nvsram using one of three storage operations . these three operations are: hardware store, activated by the hsb ; software store, activated by an address sequence; autostore, on device power down. the autostore operation is a uni que feature of quantumtrap technology and is enabled by default on the cy14b104k/cy14b104m. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 2. autostore mode figure 2 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics on page 14 for the size of the v cap . to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiat ed store cycles are performed regardless of whether a write operation has taken place. int output interrupt output . programmable to respond to the clock alarm, the watchdog timer, and the power monitor. also programmable to either active high (push or pull) or low (open drain). v ss ground ground for the device . must be connected to gr ound of the system. v cc power supply power supply inputs to the device . 3.0v +20%, ?10% hsb input/output hardware store busy : when low this output indicates that a hardware store is in progress. when pulled low external to the chip it initiates a nonvolat ile store operation. a weak internal pull up resistor keeps this pin high if not connected. (connection optional) v cap power supply autostore capacitor . supplies power to the nvsram during power loss to store data from sram to nonvolatile elements. pin definitions (continued) pin name io type description 0.1uf vcc 10kohm v cap vcc we v cap v ss [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 4 of 29 the hsb signal is monitored by the system to detect if an autostore cycle is in progress. hardware store (hsb ) operation the cy14b104k/cy14b104m provides the hsb pin to control and acknowledge the store operations. the hsb pin is used to request a hardware st ore cycle. when the hsb pin is driven low, the cy14b104k/cy14b104m conditionally initiates a store operation after t delay . an actual store cycle begins only if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the cy14b104k/cy14b104m contin ues sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it is allowed a time, t delay , to complete. however, any sram write cycles requested after hsb goes low is inhibited until hsb returns high. during any store operation, rega rdless of how it is initiated, the cy14b104k/cy14b104m c ontinues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the cy14b104k/cy14b104m remains disabled until the hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power up) during power up, or after any low power condition (v cc < v switch ), an internal recall request is latched. when v cc again exceeds the sense voltage of v switch , a recall cycle is automatically initiated and takes t hrecall to complete. software store data is transferred from the sram to the nonvolatile memory by a software address sequence. the cy14b104k/cy14b104m software store cycle is initiate d by executing sequential ce controlled read cycles from si x specific address locations in exact order. during the store cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elem ents. after a store cycle is initiated, further input and output are disabled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no store or recall takes place. to initiate the software store cycle, the following read sequence must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8fc0 initiate store cycle the software sequence may be clocked with ce controlled reads or oe controlled reads. after the sixth address in the sequence is entered, the store cycle commences and the chip is disabled. it is impor tant to use read cycles and not write cycles in the sequence, although it is not necessary that oe be low for a valid sequence. after the t store cycle time is fulfilled, the sram is activated again for read and write operations. software recall data is transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4c63 initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared; then, the nonvolatile information is transferred into the sram cells. after the t recall cycle time the sram is again ready for read and write operat ions. the recall operation in no way alters the data in the nonvolatile elements. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 5 of 29 preventing autostore the autostore function is disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore is re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual store operation (hardware or software) is issued to save the autostore state th rough subseq uent power down cycles. the part comes from the factory with autostore enabled. table 1. mode selection ce we oe a15 - a0 mode io power h x x x not selected output high z standby l h l x read sram output data active l l x x write sram input data active l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active [4,5,6] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [4,5,6] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [4,5,6] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [4,5,6] notes 4. the six consecutive address locations must be in the order listed. we must be high during all six cycles to enable a nonvolatile cycle. 5. while there are 19 address lines on the cy14b104ka/cy14b104m, only the lower 16 lines are used to control software modes. 6. io state depends on the state of oe , bhe, and ble . the io table shown assumes oe , bhe, and ble low. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 6 of 29 data protection the cy14b104k/cy14b104m prot ects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc < v switch . if the cy14b104k/cy14b104m is in a write mode (both ce and we low) at power up, after a recall, or after a store, the wr ite is inhibited until a negative transition on ce or we is detected. this protects against inadvertent writes during power up or brown out conditions. noise considerations refer cy application note an1064 . real-time-clock operation nvtime operation the cy14b104k/cy14b104m offe rs internal registers that contain clock, alarm, watchdog, interrupt, and control functions. internal double buffering of the clock and the clock or timer information registers prevents accessing transitional internal clock data during a read or write operation. double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. clock and alarm registers store data in bcd format. clock operations the clock registers maintain time up to 9,999 years in one second increments. the time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. there are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. these registers contain the time of day in bcd format. bits defined as ?0? are currently not used and are reserved for future use by cypress. reading the clock while the double buffered rtc re gister structure reduces the chance of reading incorrect data from the clock, stop internal updates to the cy14b104k/cy14b 104m clock registers before reading clock data, to prevent reading of data in transition. stopping the internal register updates does not affect clock accuracy. the updating process is stopped by writing a ?1? to the read bit ?r? (in the flags register at 0x1fff0), and does not restart until a ?0? is written to the re ad bit. the rtc registers are then read while the internal clock continues to run. within 20 ms after a ?0? is written to the read bit, all cy14b104k/cy14b104m registers are simultaneously updated. setting the clock setting the write bit ?w? (in the flag s register at 0x1fff0) to a ?1? stops updates to the cy14b104k /cy14b104m registers. the correct day, date, and time is then written into the registers in 24 hour bcd format. the time writte n is referred to as the ?base time?. this value is stored in nonvolatile registers and used in the calculation of the current time . resetting the write bit to ?0? transfers those values to the ac tual clock counters, after which the clock resumes normal operation. backup power the rtc in the cy14b104k/cy14b104m is intended for perma- nently powered operation. the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chosen for the application. when the primary power, v cc , fails and drops below v switch the device switches to the backup power supply. the clock oscillator uses very little current, which maximizes the backup time available from the backup source. regardless of the clock operation with the primary source removed, the data stored in the nvsram is secure, having been stored in the nonvolatile elements when power was lost. during backup operation, the cy14b104k/cy14b104m consumes a maximum of 300 nanoamps at 2 volts. capacitor or battery values must be chosen according to the application. backup time values based on maximum current specifications are shown in the following table. nominal times are approximately three times longer. using a capacitor has the obvious advantage of recharging the backup source each time the syst em is powered up. if a battery is used, a 3v lithium is recommended and the cy14b104k/cy14b104m sources current only from the battery when the primary power is removed. the battery is not, however, recharged at any time by the cy14b104k/cy14b104m. the battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. stopping and starting the oscillator the oscen bit in the calibration register at 0x1fff8 controls the start and stop of the oscillato r. this bit is nonvolatile and is shipped to customers in the ?enabled? (set to 0) state. to preserve the battery life when t he system is in storage, oscen must be set to ?1?. this turns of f the oscillator circuit, extending the battery life. if the oscen bit goes from disabled to enabled, it takes approximately 5 second s (10 seconds maximum) for the oscillator to start. the cy14b104k/cy14b104m has t he ability to detect oscillator failure. this is recorded in the oscf (oscillator failed bit) of the flags register at the address 0x1fff0. when the device is powered on (v cc goes above v switch ) the oscen bit is checked for ?enabled? status. if the oscen bit is enabled and the oscillator is not active, the oscf bit is set. check for this condition and then write ?0? to clear the flag. note that in addition to setting the oscf flag bit, the time registers are reset to the ?base time? (see setting the clock on page 6), which is the value last written to the timekeep ing registers. the control or calibration registers and the oscen bit are not affected by the ?oscillator failed? condition. table 2. rtc backup time capacitor value backup time 0.1f 72 hours 0.47f 14 days 1.0f 30 days [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 7 of 29 if the voltage on the backup supply (v rtccap or v rtcbat ) falls below their respective minimum le vel, the oscillator may fail, leading to the oscillator failed condition which is detected when system power is restored. the value of oscf must be reset to ?0? when the time registers are written for the first time. this initializes the state of this bit which may have become set when the system was first powered on. calibrating the clock the rtc is driven by a quartz controlled oscillator with a nominal frequency of 32.768 khz. clock accuracy depends on the quality of the crystal, usually specified to 35 ppm limits at 25c. this error could equate to +1.53 minutes per month. the cy14b104k/cy14b104m employs a calibration circuit that improves the accuracy to +1/?2 ppm at 25c. the calibration circuit adds or subtracts counts from the oscillator divider circuit. the number of times pulses are suppressed (subtracted, negative calibration) or spli t (added, positive calibration) depends on the value loaded into the five calibration bits found in the calibration register at 0x 1fff8. adding counts speeds the clock up; subtracting counts slows the clock down. the calibration bits occupy the five lower order bits in the control register 8. these bits are set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit, where ?1? indicates positive calibration and ?0? indicates negative calibration. calibration occurs within a 64 mi nute cycle. the fi rst 62 minutes in the cycle may, once per mi nute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary ?1? is loaded into the register, only the first 2 minutes of the 64 minute cycle are modified; if a binary ?6? is loaded, the first 12 are affected, and so on . therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles. that is 4.068 or ?2.034 ppm of adjustment for every calibration step in the calibration register. to determine how to set the calibration, the cal bit in the flags register at 0x1fff0 is set to ?1?, which causes the int pin to toggle at a nominal 512 hz. an y deviation measured from the 512 hz indicates the degree and direction of the required correction. for example, a read ing of 512.010124 hz indicates a +20 ppm error, which requires the loading of a ?10 (001010) into the calibration register. note that setting or changing the calibration register does not af fect the frequency test output frequency. alarm the alarm function compares user programmed values with the corresponding time of day values. when a match occurs, the alarm event occurs. the alarm drives an internal flag, af, and may drive the int pin if desired. there are four alarm match fields . they are date, hours, minutes, and seconds. each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field is used in the match process. depending on the match bits, the alarm can occur as specifically as one particular second on one day of the month, or as frequently as once per second continuously. the msb of each alarm register is a match bit. selecting none of the match bits (all 1s) indicates that no match is required. the alarm occurs every second. setting the match select bit for seconds to ?0? causes the logic to match the seconds alarm value to the current time of day. since a match occurs for only one value per minute, the alarm occurs once per minute. similarly, setting the seconds and minutes match bits causes an exact match of these values. thus, an alarm occurs once per hour. setting seconds, minutes, and hours causes a match once per day. lastly, selecting all match values causes an exact time and date match. selecting other bit combinations does not produce meaningful results; however, the alarm circuit must follow the functions described. there are two ways to detect an alarm event: by reading the af flag or monitoring the int pin. the af flag in the flags register at 0x1fff0 indicates that a date or time match has occurred. the af bit is set to ?1? when a match occurs. reading the flags or control register clears the alarm flag bit (and all others). a hardware interrupt pin may also be used to detect an alarm event. watchdog timer the watchdog timer is a free running down counter that uses the 32 hz clock (31.25 ms) derived from the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register. the counter consists of a loa dable register and a free running counter. on power up, the watchdog timeout value in register 0x1fff7 is loaded into the counter load register. counting begins on power up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to ?1?. the counter is compared to the terminal value of 0. if the counter reaches this value, it causes an internal fl ag and an optional interrupt output. the timeout interrupt is prevented by setting wds bit to ?1? before the counter reaches ?0?. this causes the counter to reload with the watchdog timeout value and get restarted. as long as the wds bit is set before the counter reaches the terminal value, the interrupt and flag never occurs. new timeout values are written by setting the watchdog write bit to ?0?. when the wdw is ?0? (from the previous operation), new writes to the watchdog timeout value bits d5?d0 allow the modifi- cation of timeout values. when wdw is ?1?, then writes to bits d5?d0 are ignored. the wdw function allows to set the wds bit without concern that the watchdog timer value is modified. a logical diagram of the watchdog timer is shown in figure 3 on page 8. note that setting the watchdog timeout value to ?0? is otherwise meaningless and as a result, disables the watchdog function. the output of the watchdog timer is a flag bit wdf that is set if the watchdog is allowed to timeout. the flag is set on a watchdog timeout and cleared when the flags or control register is read by the user. the user can also enable an optional interrupt source to drive the int pin if the watchdog timeout occurs. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 8 of 29 . power monitor the cy14b104k/cy14b104m provides a power management scheme with power fail interrupt capability. it also controls the internal switch to backup power for the clock and protects the memory from low v cc access. the power monitor is based on an internal band gap reference circuit that compares the v cc voltage to various thresholds. as described in the section autostore operation on page 3, when v switch is reached as v cc decays from power loss, a data store operation is initiated from sram to the nonvolatile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source, no data is read or written and the clock functions are not available to the user. the clock continues to operate in the background. the updated clock data is available to the user after t hrecall delay (see autostore/power up recall on page 16) after v cc is restored to the device. interrupts the cy14b104k/cy14b104m provi des three potential interrupt sources. they include the watchdog timer, the power monitor, and the clock or calendar alarm. each are individually enabled and assigned to drive the int pin. in addition, each has an associated flag bit that the host processor can use to determine the cause of the interrupt. some of the sources have additional control bits that determine functional behavior. in addition, the pin driver has three bits that specify its behavior when an interrupt occurs. the three interrupts each have a source and an enable. both the source and the enable must be active (true high) to generate an interrupt output. only one source is necessary to drive the pin. the user can identify the source by reading the flags or control register, which contains the flags associated with each source. all flags are cleared to ?0? when the register is read. the cycle must be a complete read cycle (we high); otherwise, the flags are not cleared. the power monitor has two programmable settings that are explained in power monitor on page 8. after an interrupt source is active, the pin driver determines the behavior of the output. it has two programmable settings. pin driver control bits are located in the interrupt register. according to the programming selections, the pin is driven in the backup mode for an alarm interrupt. in addition, the pin is an active low (open drain) or an ac tive high (push pull) driver. if programmed for operation during ba ckup mode, it is active low. lastly, the pin can provide a one sh ot function so that the active condition is a pulse or a level condition. in one-shot mode, the pulse width is internally fixe d at approximately 200 ms. this mode is intended to reset a host microcontroller. in the level mode, the pin goes to its active polarity until the flags or control register is read by the user. this mode is used as an interrupt to a host microcontroller. the control bits are summarized as follows. watchdog interrupt enable - wie . when set to ?1?, the watchdog timer drives the int pin and an internal flag when a watchdog timeout occurs. when wi e is set to ?0?, the watchdog timer affects only the internal flag. alarm interrupt enable - aie . when set to ?1?, the alarm match drives the int pin and an internal flag. when set to ?0?, the alarm match only affects the internal flag. power fail interrupt enable - pfe . when set to ?1?, the power fail monitor drives the pin and an internal flag. when set to ?0?, the power fail monitor affects only the internal flag. high/low - h/l . when set to a ?1?, the int pin is active high and the driver mode is push pu ll. the int pin can drive high only when v cc > v switch . when set to ?0?, the int pin is active low and the drive mode is open drain. active low (open drain) is operational even in battery backup mode. pulse/level - p/l . when set to ?1? and an interrupt occurs, the int pin is driven for approximately 200 ms. when p/l is set to ?0?, the int pin is driven high or low (determined by h/l) until the flags or control register is read. when an enabled interrupt source activates the int pin, an external host can read the flags or control register to determine the cause. all flags are cleared wh en the register is read. if the int pin is programmed for level mode, then the condition clears and the int pin returns to its inactive state. if the pin is programmed for pulse mode, then reading the flag also clears the flag and the pin. the pulse does not complete its specified duration if the flags or control register is read. if the int pin is used as a host reset, then the flag s or control register must not be read during a reset. during a power on reset with no battery, the interrupt register is automatically loaded with the value 24h. this enables the power fail interrupt with an active low pulse. figure 3. watchdog timer block diagram [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 9 of 29 figure 4. rtc recommended component configuration figure 5. interrupt block diagram recommended values y1 = 32.768khz rf = 10m ohm c 1 = 0 c 2 = 56 pf legend wdf - watchdog timer flag wie - watchdog interrupt enable pf - power fail flag pfe - power fail enable af - alarm flag aie - alarm interrupt enable p/l - pulse level h/l - high/low [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 10 of 29 table 3. rtc register map register bcd format data function/range d7 d6 d5 d4 d3 d2 d1 d0 0x1ffff 10s years years years: 00?99 0x1fffe 0 0 0 10s months months months: 01?12 0x1fffd 0 0 10s day of month day of month day of month: 01?31 0x1fffc 0 0 0 0 0 day of week day of week: 01?07 0x1fffb 0 0 10s hours hours hours: 00?23 0x1fffa 0 10s minutes minutes minutes: 00?59 0x1fff9 10s seconds seconds seconds: 00?59 0x1fff8 oscen 0 cal sign calibration calibration values [7] 0x1fff7 wds wdw wdt watchdog [7] 0x1fff6 wie aie pfe 0 h/l p/l 0 0 interrupts [7] 0x1fff5 m 0 10s alarm date alarm date alarm, day of month: 01?31 0x1fff4 m 0 10s alarm hours alarm hours alarm, hours: 00?23 0x1fff3 m 10 alarm minutes alarm minutes alarm, minutes: 00?59 0x1fff2 m 10 alarm seconds alarm seconds alarm, seconds: 00?59 0x1fff1 10s centuries centuries centuries: 00?99 0x1fff0 wdf af pf oscf 0 cal w r flags [7] note 7. this is a binary value, not a bcd value. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 11 of 29 table 4. register map detail 0x1ffff time keeping - years d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of the year. lower nibble contains the value for years; upper nibble contains the value for 10s of years. each nibble operates fr om 0 to 9. the range for the register is 0?99. 0x1fffe time keeping - months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the month. lower nibble cont ains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. the range for the register is 1?12. 0x1fffd time keeping - date d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the date of the month. lower ni bble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. the range for the register is 1?31. leap years are automatically adjusted for. 0x1fffc time keeping - day d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble contains a value that correlates to day of the w eek. day of the week is a ring counter that counts from 1 to 7 then returns to 1. the user must assign meaning to th e day value, because the day is not integrated with the date. 0x1fffb time keeping - hours d7 d6 d5 d4 d3 d2 d1 d0 12/24 0 10s hours hours contains the bcd value of hours in 24 hour format. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the register is 0?23. 0x1fffa time keeping - minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. the range for the register is 0?59. 0x1fff9 time keeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble contains th e lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. the range for the register is 0?59. 0x1fff8 calibration/control d7 d6 d5 d4 d3 d2 d1 d0 oscen 0 calibration sign calibration oscen oscillator enable. when set to 1, th e oscillator is stopped. when set to 0, the oscillator runs. disabling the oscillator saves battery or capacitor power during storage. on a no-battery power up, this bit is set to 0. calibration sign determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base. calibration these five bits control the calibration of the clock. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 12 of 29 0x1fff7 watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to 1 reloads and restarts the watchdog timer. setting the bit to 0 has no effect. the bit is cleared automatically after the watchdog timer is reset. the wds bit is write only. reading it always returns a 0. wdw watchdog write enable. setting this bit to 1 masks the wa tchdog timeout value (wdt5?wdt0 ) so it cannot be written. this allows the user to strobe the watchdog without disturbi ng the timeout value. setting this bit to 0 allows bits 5?0 to be written on the next write to the watchdog register. the new value is loaded on the next internal watchdog clock after the write cycle is complete. this func tion is explained in more detail in watchdog timer on page 7. wdt watchdog timeout selection. the watchdog timer interval is se lected by the 6-bit value in this register. it represents a multiplier of the 32 hz coun t (31.25 ms). the minimum range or timeout va lue is 31.25 ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3 fh). setting the wa tchdog timer register to 0 disables the timer. these bits are written only if the wdw bit was cleared to 0 on a previous cycle. 0x1fff6 interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfie 0 h/l p/l 0 0 wie watchdog interrupt enable. when set to 1 and a watchdog timeout occurs, the watchdog timer drives the int pin and the wdf flag. when set to 0, the watchdog timeout affects only the wdf flag. aie alarm interrupt enable. when set to 1, the alarm match dr ives the int pin and the af fl ag. when set to 0, the alarm match only affects the af flag. pfie power fail enable. when set to 1, the alarm match drives the int pin and the af flag. when set to 0, the power fail monitor affects only the pf flag. h/l high/low. when set to 1, the int pin is driven active high. when set to 0, the int pin is open drain, active low. p/l pulse/level. when set to 1, the int pin is driven active (determined by h/l) by an interrupt source for approximately 200 ms. when set to 0, the int pin is driven to an active leve l (as set by h/l) until the flags or control register is read. 0x1fff5 alarm - day d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the month and the mask bit to select or deselect the date value. m match. when this bit is set to 0, the date value is used in t he alarm match. setting this bit to 1 causes the match circuit to ignore the date value. 0x1fff4 alarm - hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the mask bit to select or deselect the hours value. m match. when this bit is set to 0, the hours value is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the hours value. 0x1fff3 alarm - minutes d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm minutes alarm minutes contains the alarm value for the minutes and the ma sk bit to select or dese lect the minutes value. m match. when this bit is set to 0, the minutes value is used in the alarm match. setting th is bit to 1 causes the match circuit to ignore the minutes value. 0x1fff2 alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm seconds alarm seconds contains the alarm value for the seconds and the mask bit to select or deselect the seconds? value. table 4. register map detail (continued) [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 13 of 29 m match. when this bit is set to 0, the seconds? value is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the seconds value. 0x1fff1 time keeping - centuries d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s centuries centuries 0x1fff0 flags d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf oscf 0 cal w r wdf watchdog timer flag. this read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. it is cleared to 0 when the flags/control register is read. af alarm flag. this read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. it is cleared wh en the flags/control register is read. pf power fail flag. this read only bit is set to 1 when power falls below the power fail threshold v switch . it is cleared to 0 when the flags/control register is read. oscf oscillator fail flag. set to 1 on power up only if the oscillator is not ru nning in the first 5 ms of power on operation. this indicates that time counts are no longer valid. the user must reset this bit to 0 to cl ear this condition. the chip does not clear this flag. this bit survives power cycles. cal calibration mode. when set to 1, a 512 hz square wave is output on the int pin. when set to 0, the int pin resumes normal operation. this bit defaults to 0 (disabled) on power up. w write time. setting the w bit to 1 freeze updates of the timekeeping registers. the user can then write them with updated values. setting the w bit to 0 transfers the cont ents of the time registers to the timekeeping counters. r read time. setting the r bit to 1 copies a static image of the timekeeping registers and places them in a holding register. the user can then read them without concerns over changing values causing system errors. the r bit going from 0 to 1 causes the timekeeping capture, so th e bit must be returned to 0 before reading again. table 4. register map detail (continued) [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 14 of 29 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied ............................................ ?55 c to +150 c supply voltage on v cc relative to gnd ..........?0.5v to 4.1v voltage applied to outputs in high-z state....................................... ?0.5v to v cc + 0.5v input voltage.............................................?0.5v to vcc+0.5v transient voltage (<20 ns) on any pin to ground potential .................. ?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount pb soldering temperature (3 seconds) .......................................... +260 c output short circuit current [8] ..................................... 15 ma static discharge voltage....... ........... ............ ............ > 2001v (per mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial ?40 c to +85 c 2.7v to 3.6v dc electrical characteristics over the operating range (v cc = 2.7v to 3.6v) [10] parame- ter description test conditions min max unit i cc1 average v cc current t rc = 15 ns t rc = 20 ns t rc = 25 ns t rc = 45 ns dependent on output loading and cycle rate.values obtained without output loads. i out = 0 ma commercial 70 65 65 50 ma ma ma industrial 75 70 70 52 ma ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max. average current for duration t store 6ma i cc3 [9] average v cc current at t rc = 200 ns, 3v, 25c typical we > (v cc ? 0.2). all other i/p cycling. dependent on output loading and cycle rate. values obtained without output loads. 35 ma i cc4 average v cap current during autostore cycle all inputs don?t care, v cc = max. average current for duration t store 6ma i sb v cc standby current ce > (v cc ? 0.2).all others v in < 0.2v or >(v cc ? 0.2v). standby current level after nonvola tile cycle is complete. inputs are static. f = 0mhz. 3ma i ix input leakage current (except hsb ) v cc = max, v ss < v in < v cc ?1 +1 a input leakage current (for hsb ) v cc = max, v ss < v in < v cc ?100 +1 a i oz off state output leakage current v cc = max., v in = v ss < v in < v cc , ce or oe > v ih ?1 +1 a v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap storage capacitor between v cap pin and v ss , 5v rated 61 82 f notes 8. outputs shorted for no more than one second. only one output is shorted at a time . 9. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperat ure), and v cc = 3v. not 100% tested. 10. the hsb pin has i out =-10 ua for v oh of 2.4v. this parameter is characterized but not tested. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 15 of 29 ac test conditions input pulse levels ....................................................0v to 3v input rise and fall times (10% - 90%) ........................ < 5 ns input and output timing reference levels .................... 1.5v capacitance in the following table, the capacitance parameters are listed. [11] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0v 7pf c out output capacitance 7 pf thermal resistance in the following table, the thermal resistance parameters are listed. [11] parameter description test conditions 44 tsop ii 54 tsop ii unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 31.11 30.73 c/w jc thermal resistance (junction to case) 5.56 6.08 c/w figure 6. ac test loads 3.0v output 5 pf r1 r2 789 3.0v output 30 pf r1 r2 789 577 577 i bak [12] rtc backup current commercial 300 na industrial 350 na v rtcbat [13] rtc battery pin voltage commercial 1.8 3.3 v industrial 1.8 3.3 v v rtccap [14] rtc capacitor pin voltage commercial 1.5 3.6 v industrial 1.5 3.6 v tocs rtc oscillator time to start at minimum temperature from power up or enable commercial 10 sec at 25 c temperature from power up or enable commercial 5 sec at minimum temperature from power up or enable industrial 10 sec at 25 c temperature from power up or enable industrial 5 sec notes 11. these parameters are guaranteed but not tested. 12. from either v rtccap or v rtcbat. 13. typical = 3.0v during normal operation. 14. typical = 2.4v during normal operation. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 16 of 29 ac switching characteristics parameters description 15 ns 20 ns 25 ns 45 ns unit cypress parameters alt parameters min max min max min max min max sram read cycle t ace t acs chip enable access time 15 20 25 45 ns t rc [15] t rc read cycle time 15 20 25 45 ns t aa [16] t aa address access time 15 20 25 45 ns t doe t oe output enable to data valid 10 10 12 20 ns t oha t oh output hold after address change 3 3 3 3 ns t lzce [17] t lz chip enable to output active 3 3 3 3 ns t hzce [17] t hz chip disable to output inactive 7 8 10 15 ns t lzoe [17] t olz output enable to output active 0 0 0 0 ns t hzoe [17] t ohz output disable to output inactive 7 8 10 15 ns t pu [11] t pa chip enable to power active 0 0 0 0 ns t pd [11] t ps chip disable to power standby 15 20 25 45 ns t dbe - byte enable to data valid 10 10 12 20 ns t lzbe - byte enable to output active 0 0 0 0 ns t hzbe - byte disable to output inactive 7 8 10 15 ns sram write cycle t wc t wc write cycle time 15 20 25 45 ns t pwe t wp write pulse width 10152030ns t sce t cw chip enable to end of write 15 15 20 30 ns t sd t dw data setup to end of write 5 8 10 15 ns t hd t dh data hold after end of write 0 0 0 0 ns t aw t aw address setup to end of write 10 15 20 30 ns t sa t as address setup to start of write 0 0 0 0 ns t ha t wr address hold after end of write 0 0 0 0 ns t hzwe [17,18] t wz write enable to output disable 7 8 10 15 ns t lzwe [17] t ow output active after end of write 3 3 3 3 ns t bw - byte enable to end of write 15 15 20 30 ns autostore/power up recall parameters description cy14b104k/cy14b104m unit min max t hrecall [19] power up recall duration 20 ms t store [20] store cycle duration 15 ms v switch low voltage trigger level 2.65 v t vccrise vcc rise time 150 s notes 15. we must be high during sram read cycles. 16. device is continuously selected with ce and oe both low. 17. measured 200 mv from steady state output voltage. 18. if we is low when ce goes low, the outputs remain in the high impedance state. 19. t hrecall starts from the time v cc rises above v switch . 20. if an sram write has not tak en place since the last nonvolatil e cycle, no store takes place. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 17 of 29 software controlled store/recall cycle in the following table, the so ftware controlled store/recall cycle parameters are listed. [21, 22] parameters description 15 ns 20 ns 25 ns 45 ns unit min max min max min max min max t rc store/recall initiation cycle time 15 20 25 45 ns t as address setup time 0 0 0 0 ns t cw clock pulse width 12152030 ns t ghax address hold time 1 1 1 1 ns t recall recall duration 200 200 200 200 s t ss [23, 24] soft sequence processing time 70 70 70 70 s hardware store cycle parameters description cy14b104k/cy14b104m unit min max t delay [25] time allowed to complete sram cycle 1 70 s t hlhx hardware store pulse width 15 ns switching waveforms figure 7. sram read cycle #1: address controlled [15, 16, 26] t rc t aa t oha address dq (data out) data valid note 21. the software sequence is clocked with ce controlled or oe controlled reads. 22. the six consecutive addr esses must be read in the order listed in table 1 on page 5. we must be high during a ll six consecutive cycles. 23. this is the amount of time it takes to take action on a soft sequence command.vcc power must remain high to effectively regi ster command. 24. commands such as store and recall lock out io until operation is complete which further increases this time. see specific co mmand. 25. on a hardware store initiation, sram operation continues to be enabled for time t delay to allow read and write cycles to complete. 26. hsb must remain high during read and write cycles. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 18 of 29 figure 8. sram read cycle #2: ce controlled [15, 26, 28] figure 9. sram write cycle #1: we controlled [18, 26, 27, 28] switching waveforms (continued) address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe data valid active standby t pu dq (data out) icc t lzbe t dbe t hzbe hzoe t t hzce bhe , ble t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data bhe , ble t bw notes 27. ce or we must be > vih during address transitions. 28. bhe and ble are applicable for x16 configuration only. [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 19 of 29 figure 10. sram write cycle #2: ce controlled [18, 26, 27, 28] figure 11. autostore/power up recall [29] note 29. read and write cycles are ignored during store, recall, and while vcc is below v switch. switching waveforms (continued) t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid bhe , ble t bw v cc v switch t store t store t hrecall t hrecall autostore power-up recall read & write inhibited store occurs only if a sram write has happened no store occurs without atleast one sram write t vccrise [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 20 of 29 figure 12. ce controlled software store/recall cycle [22] figure 13. oe controlled software store/recall cycle [22] switching waveforms (continued) t rc t rc address # 1 address # 6 address t as t cw t glax t store / t recall data valid data valid high impedance ce oe dq (data) a a a a a a a a a a a a a a t rc t rc address # 1 address # 6 address t as t cw t ghax t store / t recall data valid data valid high impedance ce oe dq (data) a a a a a a a a a a a a a a [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 21 of 29 figure 14. hardware store cycle [25] figure 15. soft sequence processing [ 23, 24] switching waveforms (continued) t ss t ss [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 22 of 29 part numbering nomenclature option: t - tape & reel blank - std. speed: 20 - 20 ns 25 - 25 ns data bus: k - x8 + rtc m - x16 + rtc density: 104 - 4 mb voltage: b - 3.0v cypress cy 14 b 104 k - zs p 15 x c t nvsram 14 - autostore + software store + hardware store temperature: c - commercial (0 to 70c) i - industrial (?40 to 85c) pb-free package: zs - tsop ii p - 54 pin blank - 44 pin 45 - 45 ns 15 - 15 ns [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 23 of 29 ordering information speed (ns) ordering code package diagram package type operating range 15 cy14b104k-zs15xct 51-85087 44-pin tsopii commercial cy14b104k-zs15xit 51-85087 44-pin tsopii industrial cy14b104k-zs15xi 51-85087 44-pin tsopii cy14b104m-zs15xct 51-85087 44-pin tsopii commercial cy14b104m-zs15xit 51-85087 44-pin tsopii industrial cy14b104m-zs15xi 51-85087 44-pin tsopii cy14b104k-zsp15xct 51-85160 54-pin tsopii commercial cy14b104k-zsp15xit 51-85160 54-pin tsopii industrial cy14b104k-zsp15xi 51-85160 54-pin tsopii cy14b104m-zsp15xct 51-85160 54-pin tsopii commercial cy14b104m-zsp15xit 51-85160 54-pin tsopii industrial cy14b104m-zsp15xi 51-85160 54-pin tsopii 20 cy14b104k-zs20xct 51-85087 44-pin tsopii commercial cy14b104k-zs20xit 51-85087 44-pin tsopii industrial cy14b104k-zs20xi 51-85087 44-pin tsopii cy14b104m-zs20xct 51-85087 44-pin tsopii commercial cy14b104m-zs20xit 51-85087 44-pin tsopii industrial cy14b104m-zs20xi 51-85087 44-pin tsopii cy14b104k-zsp20xct 51-85160 54-pin tsopii commercial cy14b104k-zsp20xit 51-85160 54-pin tsopii industrial cy14b104k-zsp20xi 51-85160 54-pin tsopii cy14b104m-zsp20xct 51-85160 54-pin tsopii commercial cy14b104m-zsp20xit 51-85160 54-pin tsopii industrial cy14b104m-zsp20xi 51-85160 54-pin tsopii 25 cy14b104k-zs25xct 51-85087 44-pin tsopii commercial cy14b104k-zs25xit 51-85087 44-pin tsopii industrial cy14b104k-zs25xi 51-85187 44-pin tsopii cy14b104m-zs25xct 51-85087 44-pin tsopii commercial cy14b104m-zs25xit 51-85087 44-pin tsopii industrial cy14b104m-zs25xi 51-85087 44-pin tsopii cy14b104k-zsp25xct 51-85160 54-pin tsopii commercial CY14B104K-ZSP25XIt 51-85160 54-pin tsopii industrial CY14B104K-ZSP25XI 51-85160 54-pin tsopii cy14b104m-zsp25xct 51-85160 54-pin tsopii commercial cy14b104m-zsp25xit 51-85160 54-pin tsopii industrial cy14b104m-zsp25xi 51-85160 54-pin tsopii [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 24 of 29 45 cy14b104k-zs45xct 51-85087 44-pin tsopii commercial cy14b104k-zs45xit 51-85087 44-pin tsopii industrial cy14b104k-zs45xi 51-85187 44-pin tsopii cy14b104m-zs45xct 51-85087 44-pin tsopii commercial cy14b104m-zs45xit 51-85087 44-pin tsopii industrial cy14b104m-zs45xi 51-85087 44-pin tsopii cy14b104k-zsp45xct 51-85160 54-pin tsopii commercial cy14b104k-zsp45xit 51-85160 54-pin tsopii industrial cy14b104k-zsp45xi 51-85160 54-pin tsopii cy14b104m-zsp45xct 51-85160 54-pin tsopii commercial cy14b104m-zsp45xit 51-85160 54-pin tsopii industrial cy14b104m-zsp45xi 51-85160 54-pin tsopii all parts are pb-free. the above table contains preliminary info rmation. please contact your local cypress sales representative for availability of these parts. ordering information (continued) speed (ns) ordering code package diagram package type operating range [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 25 of 29 package diagrams figure 16. 44-pin tsop ii (51-85087) max min. dimension in mm (inch) 11.938 (0.470) plane seating pin 1 i.d. 44 1 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) ejector pin r g o k e a x s 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) base plane 0.10 (.004) 22 23 top view bottom view 51-85087-*a [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 26 of 29 figure 17. 54-pin tsop ii (51-85160) package diagrams (continued) 51-85160-** [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 27 of 29 document history page document title: cy14b104k/cy14b104m 4 mbit (512k x 8/256k x 16) nvsram with real-time-clock document number: 001-07103 rev. ecn no. submission date orig. of change description of change ** 431039 see ecn tup new data sheet *a 489096 see ecn tup removed 48 ssop package added 44 tsopii and 54 tsopii packages updated part numbering nomenclature and ordering information added soft sequence processing time waveform added rtc characteristics table added rtc recommended component configuration *b 499597 see ecn pci removed 35ns speed bin added 55ns speed bin. updated ac table for the same changed ?unlimited? read/write to ?infinit e? read/write features section: changed typical i cc at 200-ns cycle time to 8 ma changed store cycles from 500k to 200k cycles. shaded commercial grade in operating range table. modified icc/isb specs. changed v cap value in dc table added 44 tsop ii in thermal resistance table modified part nomenclature table. chang es reflected in the ordering information table. *c 517793 see ecn tup removed 55ns speed bin changed pinout for 44tsopii and 54tsopii packages changed i sb to 1ma changed i cc4 to 3ma changed v cap min to 35 f changed v ih max to vcc + 0.5v changed t store to 15ns changed t pwe to 10ns changed t sce to 15ns changed t sd to 5ns changed t aw to 10ns removed t hlbl added timing parameters for bhe and ble - t dbe , t lzbe , t hzbe , t bw removed min. specification for vswitch changed t glax to 1ns added t delay max. of 70us changed t ss specification from 70us min. to 70us max. *d 825240 see ecn uha changed the data sheet fr om advance information to preliminary changed t dbe to 10ns in 15ns part changed t hzbe in 15ns part to 7ns and in 25ns part to10ns changed t bw in 15ns part to 15ns and in 25ns part to 20ns changed t glax to t ghax changed the value of i cc3 to 25ma changed the value of t aw in 15ns part to 15ns *e 914280 see ecn uha changed the figure-14 title from 54-pb to 54 pin included all the information for 45ns part in this data sheet [+] feedback
preliminary cy14b104k/cy14b104m document #: 001-07103 rev. *i page 28 of 29 *f 1890926 see ecn vsutmp8/a esa added footnote 1, 2 and 3. updated logic block diagram updated pin definition table changed 8mb address expansion pin from pin 43 to pin 42 for 44-tsop ii (x8) package. corrected typo in v il min spec changed the value of i cc3 from 25ma to 13ma changed i sb value from 1ma to 2ma updated ordering information table rearranging of footnotes. changed package diagrams title. the pins x1 and x2 interchanged in 44tsop ii(x8) and 54tsop ii(x16) pinout diagram. *g 2267286 see ecn gvch/pyr s rearranging of ?features? added bhe and ble information in pin definitions table updated figure 2 (autostore mode) updated footnote 6 rtc register map:register 0x1fff6:changed d4 from abe to 0 register map detail:0x1fff6:changed d4 from abe to 0 and removed abe infor- mation changed i cc2 & i cc4 from 3ma to 6ma changed i cc3 from 13ma to 15ma changed i sb from 2ma to 3ma added input leakage current (i ix ) for hsb in dc electrical characteristics table changed vcap from 35uf min and 57uf max value to 54uf min and 82uf max value corrected typo in t dbe value from 22ns to 20ns for 45ns part corrected typo in t hzbe value from 22ns to 15ns for 45ns part corrected typo in t aw value from 15ns to 10ns for 15ns part changed vrtccap max from 2.7v to 3.6v changed trecall from 100 to 200us added footnote 10, 29 reframed footnote 18, 25 added footnote 18 to figure 8 (sram write cycle #1) added footnote 18, 26 and 27 to figure 9 (sram write cycle #2) *h 2483627 see ecn gvch/pyr s removed 8 ma typical i cc at 200 ns cycle time in feature section referenced footnote 9 to i cc3 in dc characteristics table changed i cc3 from 15 ma to 35 ma changed vcap minimum value from 54 uf to 61 uf changed t avav to t rc changed v rtccap minimum value from 1.2v to 1.5v figure 12:changed t sa to t as and t sce to t cw document title: cy14b104k/cy14b104m 4 mbit (512k x 8/256k x 16) nvsram with real-time-clock document number: 001-07103 rev. ecn no. submission date orig. of change description of change [+] feedback
document #: 001-07103 rev. *i revised june 20, 2008 page 29 of 29 autostore and quantumtrap are registered trademarks of simtek corporation. all products and company names mentioned in this doc ument are the trademarks of their respective holders. preliminary cy14b104k/cy14b104m ? cypress semiconductor corporation, 2006-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb *i 2519319 06/20/08 gvch/pyr s added 20 ns access speed in ?features? added i cc1 for trc=20 ns for both industrial and commecial temperature grade updated thermal resistance values for 44-tsop ii and 54-tsop ii packages added ac switching characteristics specs for 20 ns access speed added software controlled store/recall cycle specs for 20 ns access speed updated ordering information and part numbering nomenclature document title: cy14b104k/cy14b104m 4 mbit (512 k x 8/256k x 16) nvsram with real-time-clock document number: 001-07103 rev. ecn no. submission date orig. of change description of change [+] feedback

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